A typical multiprocessing computer system consists of operating system software residing in main memory running on at least one of two or more microprocessors executing code in parallel that share both a common memory access bus as well as an inter-processor communication bus.
Two types of microprocessors are commonly used to implement a multiprocessing computer system: Complex Instruction Set Computer (CISC) processors or Reduced Instruction Set Computer (RISC) processors. Both types of processors operate by fetching native machine instructions from memory, decoding them, and then executing those instructions in sequential order. Each step in the process of completing an instruction consumes clock cycles. The same cumulative number of clock cycles will be consumed each time the same sequence of instructions is completed.
Virtually any computer algorithm can be implemented through the correct sequencing of instructions which are encoded in the native machine language of the particular CISC or RISC processor targeted to execute that sequence. This sequence of encoded instructions residing in memory is essentially a representation of the algorithm itself. Therefore, any type of processor having access to the block of memory containing the instruction sequence, and having the capability of decoding the sequence, can potentially implement the algorithm even though it may not have been the original processor targeted to execute the sequence.
Alternatively, a computer algorithm can be implemented by constructing a finite state machine through the correct configuration of one or more re-configurable logic devices. A well known example of a re-configurable logic device is a Field Programmable Gate Array (FPGA). A typical re-configurable logic device contains an array of both simple and complex logic elements, as well as, registers. The configuration information is stored in memory in the form of an encoded bit map. This bit map residing in memory essentially represents the finite state machine and therefore the algorithm itself.
A re-configurable logic device only has to fetch and decode the configuration bit map once to construct any finite state machine whose existence will persist until re-programmed. For a given algorithm, a finite state machine typically requires significantly fewer clock cycles to execute as compared to a microprocessor executing a sequence of instructions. The ability of a re-configurable logic device to implement computer algorithms depends on the variety, complexity and quantity of logic elements available to configure.